Memory devices are important components of many integrated circuits or products having integrated circuits. Because memories are so significant to the operation of these devices, it is important that data stored in a memory device can be correctly accessed. Data can be written to a memory and read from a memory using a single clock signal. Such memories enable synchronous data transfers. Data could also be asynchronously transferred in memory devices which receive data and output data using two separate asynchronous clocks. Asynchronous clocks not only have a different phase, but also have a different frequency.
Memory devices also have various protocols for outputting stored data. For example, a first-in first-out (FIFO) memory is a memory device where a data sequence is written to and retrieved from the memory in exactly the same order. No explicit addressing is required, and the write and read operations can be completely independent and use unrelated clocks. While the concept of a FIFO is simple, the implementation of an asynchronous FIFO is often difficult. One common implementation of an asynchronous FIFO is a random access memory (RAM) having two independently clocked ports (i.e. one for writing and one for reading), and two independent address counters to steer write and read data. However, synchronizing and decoding the two ports operating at two asynchronous frequencies can require significant engineering effort.
In particular, asynchronous FIFOs commonly include signals indicating the extreme conditions of the FIFO, such as empty or full. Even experienced designers have had problems decoding these two conditions in a fail-safe way. Synchronization is difficult when the FIFOs operate with two independent clocks of several hundred megahertz (MHz). When the last data entry is being read, an EMPTY signal goes active (e.g. goes “high”) after a read clock reads the final data. The read enable signal must then be inactive until the EMPTY signal has gone inactive or “low” again.
Unlike a synchronous FIFO where both the rising and the falling edge of the EMPTY signal are synchronous with the common clock, the rising and falling edges of an EMPTY signal of an asynchronous FIFO are not synchronous with a single clock. That is, the EMPTY signal can only be caused by a read operation, and therefore, the leading edge is naturally synchronous with the read clock. However, the trailing edge is caused by a write operation, and therefore is synchronous with the write clock. According, it is necessary to move the trailing edge of the EMPTY signal to the read clock domain. A variety of techniques for moving the trailing edge to the read clock domain could be used, including the common technique of using synchronizing flip-flops. However, such techniques might create metastability.
Considerable design effort is spent and additional circuitry is used to manipulate the trailing edge of the EMPTY signal so that it is moved to the read clock domain. However, testing a FIFO for reliable operation requires determining that the clock synchronization circuit for the two clock signals, which can have an infinite number of timing relationships, will successfully transfer the trailing edge of the EMPTY signal to the read clock domain. On the other hand, a manufacturer wants to test the FIFO thoroughly, but in a limited time, such as a few seconds.
Accordingly, there is a need for a circuit and method of testing a memory device to ensure that a circuit for moving a clock signal to a different clock domain is functioning properly.